In recent years, a demand of a nonvolatile memory is increased as a rewritable semiconductor memory device. In a flash memory that is a typical example of the nonvolatile memory, one using a floating gate is the mainstream, but it is considered that it is difficult to make a tunnel gate oxide film be miniaturized, and it is also considered that the miniaturization is approaching miniaturization limit thereof.
As a technique to overcome this miniaturization limit, a trap type semiconductor memory device has received high attention recently. In the trap type semiconductor memory device, an insulation film having a trap level is formed on a tunnel gate oxide film formed on a semiconductor substrate. Information is stored by capturing an electrical charge at the trap level that exists in this insulation film.
As a representative example of the trap type semiconductor memory device in which the trap level in the insulation film is a storage node, an MNOS (Metal-Nitride-Oxide-Semiconductor) memory and an MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memory are mentioned. In the MNOS memory and the MONOS memory, a silicon nitride film (N) is used as an insulation film having a trap level.
A structure and a programming method of the MONOS type semiconductor memory device are disclosed in Japanese Patent Application Publication No. 2001-156189 (Patent Document 1), for example. The structure and an operation method of the semiconductor memory device disclosed in Patent Document 1 will be explained briefly using FIG. 18.
An MONOS type semiconductor memory cell 50 disclosed in Patent Document 1 is constructed as follows. As shown in FIG. 18, n type first and second impurity diffused layers 52, 53 that are to respectively become source and drain regions of the semiconductor memory cell 50 are formed in a p type silicon substrate 51. A silicon dioxide film 54 is formed on the silicon substrate 51, and a silicon nitride film 55 that is an electrical charge accumulation layer is formed on the silicon dioxide film 54. A silicon dioxide film 56 is formed on the silicon nitride film 55, and a gate electrode 57 made of polysilicon is formed thereon. A boron implant 58 is then formed at a channel region side of each of the first and second impurity diffused layers 52, 53. The silicon dioxide film 54—the silicon nitride film 55—the silicon dioxide film 56 forms an insulation structure of the MONOS type semiconductor memory cell, which is called as ONO. The semiconductor memory cell 50 getting the above structure has a MIS type transistor structure in which the ONO as an insulation structure (I) is put between the silicon substrate 51 that is a semiconductor and the gate electrode 57.
A writing operation using channel hot electrons (Channel Hot Electron; CHE) of the MONOS type memory cell shown in FIG. 18 will be described. In the CHE, writing is carried out by applying voltage of specific voltage or more between the first and second impurity diffused layers 52, 53 that are source and drain regions, and further applying voltage of specific voltage or more to the gate electrode 57. According to the CHE, hot electrons are locally generated in the vicinity of the second impurity diffused layer 53 that is the drain region. However, electrons that can get over an energy barrier of the silicon dioxide film 54 reach the silicon nitride film 55, and are captured at discrete trap levels in the silicon nitride film 55. In this element structure, by changing voltage to be applied to a pair of source and drain regions (52, 53), it is possible to selectively realize local writing to the trap levels near the first impurity diffused layer 52 and the trap levels near the second impurity diffused layer 53 in the silicon nitride film 55. A 2-bit storing operation can be carried out in a one-transistor type semiconductor memory cell 50 in this way. On the other hand, an erasing operation is carried out by implanting hot holes generated in the vicinity of the first impurity diffused layer 52 or the second impurity diffused layer 53 due to interband tunneling to the silicon nitride film 55 to neutralize the accumulated electrons. The hot holes are generated by applying voltage of specific voltage or more between the source and drain regions (52, 53), and further applying negative voltage whose absolute value is specific voltage or more to the gate electrode 57.
In the memory cell disclosed in Patent Document 1, by providing boron implants 58 at junctional portions of the source and drain regions, a region in which electric field intensity is heightened is formed near the drain region of a channel region at writing/erasing, whereby a difference between an implantation region of the hot electrons and an implantation region of the hot holes in the silicon nitride film 55 is to be reduced. Thus, even though the programming cycle number is increased, it avoids increasing the amount of remaining electrons in the silicon nitride film 55 after erasing.
In this regard, the writing and erasing method disclosed in Patent Document 1 is one using hot electrons and hot holes, but other than the method, for example, there is a method of applying voltage of specific voltage or more between the silicon substrate 51 and the gate electrode 57, implanting electrons or holes by means of Fowler-Nordheim (FN) tunnel at writing and drawing electrons or holes by means of the FN tunnel at erasing. However, 2-bit writing that takes advantage of locality of the trap levels in the silicon nitride film 55 cannot be carried out by means of FN tunnel writing.